Non-volatile memory is a type of memory that preserves data with or without power applied to the memory. Most computer and electronic systems use a binary number system with bits. Two distinctly different current levels that flow through the memory under the correct conditions represent each bit, a one or a zero.
Some memory is single-level, where one bit of information is stored in each memory cell. In order to determine the value of the memory cell, current through the memory cell is compared to a reference memory cell. A current through the memory cell that is higher than that through the reference cell represents a bit value (e.g. one), while a current through the memory cell that is lower than that through the reference cell represents the other bit value (e.g. zero).
FIG. 1 is a schematic diagram illustrating a conventional memory system 10. The system 10 includes memory cell 12, which stores data. In order to read the data out, current through memory cell 12 is compared with current though reference memory cell 14. Whether the current through memory cell 12 is higher or lower than current through reference memory cell 14 determines the bit value stored in memory cell 12.
During a read sequence, for example, of system 10, reference memory cell 14 is biased to an appropriate voltage level by transistor 16, causing current “I” to travel through transistor 16 and cell 14. Transistor 18 and transistor 20 are in a current mirror configuration, whereby current passing through transistor 18 is “mirrored” with current passing through transistor 20. The amount of current through transistor 20 is relative to the amount of current through transistor 18 in approximately the same ratio as the gate width of transistor 20 to the gate width of transistor 18. A wider gate in transistor 20 will result in more current passing through transistor 20 than transistor 18. In one example, transistor 20 has a gate that is “n” times larger than the gate of transistor 18, therefore the current drawn through transistor 20 is “nI.” This may be done in order to more rapidly charge capacitor 21.
Memory cell system 22 is one of many cells (not shown) connected to reference memory cell 14. Each of cell systems 22 includes a memory cell. In order to compare current through reference memory cell 14, transistors 24 and 26 form another current mirror, with current passing through transistor 24 mirrored by current drawn through transistor 26. Capacitor 21 biases transistor 26, causing a current “I,” which is close to the same current level “I” through transistor 14.
Transistors 28 and 30 form another current mirror, however current “I” is not mirrored through memory cell 12. Rather, transistor 32 biases transistor 12 and in conjunction with load 34 creates a current “I*” that is relative to the value stored in memory cell 12.
Sense amplifier 36 compares the voltage at point 38 with the voltage at point 40 and based on that comparison, the bit value stored in memory cell 12 may be determined.
One problem with the conventional system 10 is that the current mirrors created by transistors 18 and 20, and 24 and 26 introduce error currents (Early effect) because there is a voltage mismatch between the transistors in the mirror. In other words, the current mirror does not mirror current perfectly from one side to the other. Sense amplifier 36 compares voltage at point 40 to voltage at point 38, including the errors produced in current by the current mirrors. Rather than comparing voltage across memory cell 12 with the actual voltage across reference memory cell 14, there is an error imparted by the current mirrors. The margin for error in determining a bit value from memory cell 12 is decreased when error is introduced into system 10 through the current mirrors.
Therefore, in a single-level memory there is some decrease in the margin for error. However, some memory is multi-level, having more than one bit in each memory cell. Multiple bits require multiple levels of current to represent the bits, further reducing the margin for error in reading memory cells. The margin for error is more limited in multi-level memory than in single-level memory.
Accordingly, what is needed is a system and method for preserving the margin for error in memory. The present invention addresses such a need.